Combining digital logic and radio-frequency (RF) circuits on the same integrated circuit (IC), or even printed circuit board (PCB), introduces the likelihood of the digital logic interfering with radio operations. More specifically, the energy of the interference at certain frequencies, such as harmonics of the digital clock frequency, can appear to an RF receiver as an in-band signal that may interfere with actual incoming (or even transmitted) radio signals at or near those frequencies. Several conventional techniques exist for combating the interference, are known to persons of ordinary skill in the art, and are therefore briefly described below.
FIGS. 1A-1B show, respectively, a conventional digital synchronizer used to modulate digital clock edges, and associated timing signals. As seen in FIG. 1B, although the average frequency of the resulting FRETIMED clock is not altered, edges of that clock are moved to align with edges of FLO. Doing so changes the harmonics of the resulting digital clock to generate less interference in an RF band based on FLO. The retimed output can exhibit shorter times between adjacent edges than the original clock. The minimum retimed edge-to-edge delay for the example above is given by:
      T          MIN              RETIMED                  E          ⁢                                          ⁢          2          ⁢          E                      =            INT      ⁡              (                              T                          MIN                              CLK                                  E                  ⁢                                                                          ⁢                  2                  ⁢                  E                                                              ·                      F            LO                          )                    F      LO      where TMIN_CLK—E2E is the minimum edge-to-edge time for the clock frequency, FCLK, and FLO represents a local oscillator frequency of an RF receiver. Because of the integer function, INT( ), which truncates its parameter to an integer smaller than or equal to the parameter, the minimum retimed edge-to-edge time is generally less than the original edge-to-edge time. If the duty-cycle of the original clock is not close to 50%, and the FLO is not very much larger than FCLK, the retimed edge-to-edge time can be significantly shorter than TMIN_CLK—E2E. This may result digital logic running from the retimed clock and having critical signal paths between registers clocking on opposite clock edges to be capable of running at a much faster speed than if running from the original clock, FCLK. The digital logic's increased frequency may increase both power and area (on an IC) of the digital logic.